Like digital transistors, analog transistors have been available in decreasing sizes over time with transistor channel lengths that formerly were tens of thousands of nanometers being reduced a thousand-fold to a hundred nanometers or less in length. However, maintaining transistor quality and electrical characteristics for such downwardly scaled analog transistors is difficult at nanometer scales and can even be difficult for larger analog transistors useful in ultra-low signal or low noise applications. This is particularly true for mixed signal die that support both analog and digital transistors. Digital transistors and circuits benefit from design and processes that encourage tightly controlled on/off transistor switching while analog circuits often require transistors with linear response over a wide range of input/output conditions, improved Rout, or other electrical characteristics. In addition, analog circuits greatly benefit from analog transistors that have low thermal, shot, flicker, and/or burst noise levels as compared to transistors suitable for digital circuits and by analog transistor pairs (i.e. differential pair transistors) that have closely matched electrical properties, including in particular current-voltage response curves and threshold voltage.
Accordingly, cost effective transistor structures and manufacturing processes are needed for CMOS analog transistors alone or in combination with digital CMOS transistors. Such analog transistors must be reliable at nanometer scales and should not require expensive or unavailable tools or process control conditions. While it is difficult to balance the many variables that control transistor electrical performance, particularly when both analog and digital transistors must be manufactured on the same die with compatible processes, finding suitable transistor dopant structures and manufacturing techniques that result in acceptable noise and electrical characteristics are commercially valuable and necessary.
Having low noise and low variation in transistor characteristics is particularly useful for amplifier circuits. In a multistage analog amplifier circuit, noise output from the final stage can be almost entirely determined by noise generated in the initial stage of the analog amplifying transistors. Such noise created by the initial amplifying stage is carried along and amplified in later stages and can require incorporation of expensive hardware or software to support intensive filtering or noise rejection/compensation techniques. In another example, sense amplifiers are commonly used in digital solid state integrated circuit (IC) applications which require low voltage sensing. Sense amplifiers can be used in memory read circuits for memory bit sensing, in bus signal receivers, and interfacing with low voltage data paths in a processor. Typically, sense amplifiers are formed in the same IC die as the memory storage array and the processor data path. Normally, the inputs are considered analog while the outputs of a sense amplifier being full swing voltages can be digital. Such a conventional sense amplifier at its input has a source coupled matched differential pair, an active load such as a regenerative circuit to provide a full swing, and a current sink or source. However, as gate length and overall dimensions of transistors forming the input pair decrease, variations in the threshold voltage Vt of the input FETs also increases. This leads to increased offset voltages in the input pair and the active load which reduces the sensitivity of the sense amplifier and again increases cost to create additional amplifying or noise rejection circuitry.
Transistor mismatch is of particular concern for systems on a chip (SoC) or other CMOS die having a bandwidth inversely proportional to the device capacitance. As more SoC require greater bandwidth for increasing communication requirements, more SoC analog circuitry is moving towards using logic type transistor devices for high-bandwidth applications since these devices are significantly smaller and hence have much smaller capacitance. However, while bandwidth increases as the size of the devices shrink, so does the Vt mismatch between identical devices. This Vt variation can result from process variations in line etch roughness, oxide thickness, or gate granularity but can also result from more fundamental limitations such as random dopant fluctuations in nanometer sized channels. Unfortunately, Vt mismatch in small devices effectively reduces the headroom which the devices have to operate and can render the circuit useless. In order to achieve high-bandwidth SoC devices, Vt mismatch and especially random dopant fluctuations need to be controlled and reduced.